1. Field of the Invention
The present invention relates to integrated circuit (IC) devices, and particularly to a semiconductor package with reduced warpage problem and improved thermal enhancement.
2. Description of the Related Art
A typical ball grid array (BGA) semiconductor package includes a semiconductor chip mounted on an upper surface of an insulating printed circuit board substrate. The substrate may be made of a glass fiber filled organic laminate, such as FR4 board, FR5 board, or BT board, and have interconnected conductive circuit patterns on upper and lower surfaces thereof. A hardened encapsulating material covers the chip, the upper surface of the substrate, and electrical conductors, such as bond wires, that extend between the chip and the circuit patterns on the upper surface of the substrate. Conductive balls or other input/output terminals are formed on the circuit patterns of the lower surface of the substrate.
Consistent with the trend toward smaller and thinner packages, one difficulty with such a BGA semiconductor package, however, is warpage of the semiconductor package due in part to temperature cycling during the manufacturing process and differences in the thermal expansion properties of the various materials of the package, e.g., differences in the thermal expansion properties of the substrate and encapsulating material. Where the package substrate is warped, the conductive balls or other input/output terminals on the lower surface of the substrate are uneven. This causes difficulty when mounting the package onto a motherboard. The magnitude of the warpage tends to increase as package size increases, and thus tends to impose an upper limit to the size of the package. Another emerging desire is to increase the thermal performance of package as power density is getter higher along the shrinkage of advanced wafer process node. In order to keep IC's functionality and reliability, IC's power consumption is required to be compliant with power limit of the package utilized, and thus restrict the function complexity of IC due to power limitation.